The NSW's SystemC Solution
Why do we need H/W implementation skill for using SystemC high level synthesis tool?
HLS tool does not care regarding hardware architecture.
Therefore implementing algorithm into the hardware, need to reconstruct the structure of processes by rewriting source code. This process is not executed by HLS today.
Making close between the algorithm which is developed and evaluated by H/W implementation and developing hardware.
Reconstruction process e.g. rewriting process is separated with algorithm development side and hardware development side because language specification and notation is optimized for each objects in general.
With linking those two major processes, you can avoid to translate and rewrite errors of the inheritance of algorithm by different languages. Then the development cycle of the hardware will be developed with effect with lowest human errors risks.
1.More perfect optimization in the algorithm and H/W implementation.
To evaluate algorithm in real hardware will accelerate to improve processing the result.
The other hand, implementing algorithm into hardware with optimization is huge engineering effort.
Still big effort in hardware implementation using SystemC HLS. but linking with algorithm development engineers and hardware engineers and inheriting the algorithm will enable to do more perfect optimization in the development phase.
2.The issues of H/W development using evolutionally algorithm is under developing and evaluating, additionally need to evaluate and modifying algorithm operating on the real device or product.
The value of product is definitely made by processing algorithm.
Therefore, the evaluating algorithm is the most important in developing the product, but the implementing effort takes too long time with much bigger load in hardware development phase with creating implementation specification to simulated RTL source.
The reason is a technology gap between software language such as C/C++ and other and the hardware language as RTL; Verilog or VHDL.
The C/C++ does not synthesis the hardware logic diagram, therefore in developing hardware, the algorithm would be rewrite the hardware implementation specification followed by writing RTL code using Verilog or VHDL and others.
SystemC is getting great change for generating hardware logic directly form algorithm notation by C/C++ software language.
But SystemC does not care about the architecture of hardware implementation such as micro architecture and more deep physical issues using gates count, operational speed and limitation of calculation accuracy.
SystemC enable to evaluate the algorithm in real device or product and implement faster into hardware. But rewrite C/C++ source to SystemC need the hardware engineering experience.
3.Collaborated work with algorithm developer and hardware implementer will accelerate evaluating algorithm optimizing for the value of product and optimization of device implementation.
Used to be the traditional methodology of algorithm implementation into hardware linked algorithm side and hardware side by the implementation specification.
The approach has large propagation delay in modification of algorithm into hardware.
Especially regarding implement of architecture modification has much larger effort, so some time could not modify implementation for improve processing result.
4.The traditional hardware development flow
Major Process
1)Create the specification of hardware implementation by natural language
2)Develop RTL source from the hardware implementation specification
3)Simulate RTL code
4)Evaluate RTL with simulation in device configuration.
5)Evaluate functions in ES chip, that after backend design process and produce real chip.
Major Issues
1)There are big risks in translation specification and evaluating algorithm in RTL code.
2)Too difficult discussing regarding evaluating result of RTL code with RTL engineer and algorithm development engineer.
3)It needs so long time to modify RTL code based on algorithm change from evaluating result.
5.NSW SystemC design flow for algorithm based hardware logic
Solutions for major issues.
1)Remove making hardware implementing specification
2)Enable to be friendlier and discuss about the hardware implementation and modification algorithm closely with algorithm engineer and hardware implement engineer.
3)Enable avoid rework risk of backend process with evaluating and improving algorithm before start backend work.
4)There is providing hardware implementation skill and big work loading, that will be much help for developing hardware device with specific algorithm.
6.What is the solution for SystemC using the hardware development?
NSW SystemC Solution provides
1)To remove the step of hardware implementation specification.
a.There is a risk of translating or remade the specification by different languages, when removeing this step reduce a risk of implementation of algorithm.
b.By hardware engineer, remade the architecture of processing algorithm for hardware by modifying C/C++ source code.
c.Therefore reduce a risk of translating, and hardware engineer will be able to focus on implementing effort with hardware specific issues.
2)Supply hardware implementing effort and skills
a.Hardware design needs the hardware specific knowledge and skills such as fix bit length calculation circuit, parallel processing architecture for hardware operation speed limitation / requirement, and minimized memory space using and so on.
b.Those work needs huge engineering resource and longer term schedule.
c.NSW able to supply those resources for developing hardware device with evolutionally algorithm.
3)Tightly coupled design and evaluating in the algorithm and hardware implementing phase.
a.SystemC could be understating notation by algorithm engineer, because SystemC inheritance of heart of algorithm likely as C/C++.
b.High Level Synthesis tools help evaluating algorithm modification by algorithm engineer using FPGA based on evaluation environment, because HLS immediately synthesis RTL code and implement into FPGA.
c.Concurrently, hardware engineer will be able to optimize modification for hardware architecture based on request from algorithm engineer and result of FPGA.
d.Therefore corroboration work with algorithm and hardware engineer will make best optimization and validation executing algorithm by hardware device and system.
7.Who will get benefit by NSW SystemC solution?
NSW SystemC solution is basically hardware design solution. So if the software engineers who think algorithm has the idea or plan to use hardware device in the product, NSW help you design hardware device with your evolutional algorithm.
a.Algorithm / Software engineer who has developing or developed algorithm source code by C/C++.
b.They need to use own algorithm, product or system to accelerate with hardware.
c.Hardware developing division who has not influence engineering resource for developing device from algorithm source code.
■ Contact
NIPPON SYSTEMWARE CO., LTD. (NSW)
Product Solutions Group, Sales Division
2-15, Nanpeidai-cho, Shibuya-ku, Tokyo 150-0036, Japan
TEL: 03-4335-2610 FAX: 03-4335-2651
E-mail: Embedded-Info@gw.nsw.co.jp
