FPGA image processing

We offer the sharpening image and clean Full hi-vision movie without haze or fog with FPGA implementation.

■Example of implementation of image processing to FPGA.


1. High-Speed processing by Hardware implementation.

The image processing algorithm is implemented to hardware that enables the real time processing video stream with less power than software solution. NSW provides Haze Reduction hardware IP for implementing FPGA device with generated binary format. Haze Reduction is processing video stream with scan line buffer that implemented itself, if customer needs the external frame memory then we provide using the external frame buffer version of Haze Reduction IP module.













System Configuration Example that Haze Reduction process direct video input stream.
(Using scan line buffer)













Input: HDMI
Output: HDMI

Extended example: Automatic parameter selection, Parameter automatic adjustment

Implementation Demo System
There are two sample implementation of HDMI I/O for Xilinx FPGA and as DVI I/O for Altera FPGA.


2. Example of Haze Reduction in the network camera.

It’s going to be the degraded quality image in the transmission compressed video, of course, although it’s possible to store the movie on the host system and remove the haze or fog with image processing.
As this solution, you can get the less debased image with processing input signal as early as possible.

It is suitable implementation by FPGA to process the big size movie as it is possible to implement to hardware.


•Can be effectively utilized sensor resolution
• Real-time processing
Video processing low-latency
• Sharp processing of video compressed

■Haze Reduction Specification

【Basic Specification】

INPUT RGB 8 to 12 bit
OUTPUT RGB 8 to 12 bit
Clock and Synchronous Signals

Parameter control, BUS interface.

※You need the bridge for your system BUS as BUS interface of RTL port is general-purpose BUS.


【Implementation Option】

Composition processing buffer.
Least line buffer or Frame buffer.

※You possible to optimize the structure of hardware in combination for application.



【Supply configuration】

■RTL Module
Embedded IP by RTL

■FPGA Module(negotiable)
- You should set down the target Device.
- Altera
- Xilinx
- We supplies it as Library for implementation.

■System designing model

Interface with C language or System C.


 ■Security or surveillance camera
- Improving the visibility: reducing haze or fog.
- Frontend and Backend camera of vehicles.
Monitoring camera with improving visibility the sudden haze or fog.

■Observing the view how blurry it is by ON/OFF of Haze Reduction
- Select the combination of processes for how blurry it is .

■Demo and evaluation
We are ready to support the Demo and evaluation SW for kicking start about it.
Please give us a call to the following contact.



■ Contact

Product Solutions Group, Sales Division
2-15, Nanpeidai-cho, Shibuya-ku, Tokyo 150-0036, Japan
TEL: 03-4335-2610 FAX: 03-4335-2651

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